212 search results - page 10 / 43 » The Impact of Memory Models on Software Reliability in Multi... |
SIGOPS
2010
13 years 1 months ago
2010
Modern chip-level multiprocessors (CMPs) contain multiple processor cores sharing a common last-level cache, memory interconnects, and other hardware resources. Workloads running ...
DATE
2004
IEEE
13 years 10 months ago
2004
IEEE
We present the design exploration of a System-on-Chip architecture dedicated to the implementation of the HIPERLAN/2 communication protocol. The task was accomplished by means of ...
EUROSYS
2007
ACM
14 years 4 months ago
2007
ACM
Software transactional memory (STM) is a promising technique for controlling concurrency in modern multi-processor architectures. STM aims to be more scalable than explicit coarse...
GTTSE
2007
Springer
14 years 1 months ago
2007
Springer
With the increase of amount of transistors which can be contained on a chip and the constant expectation for more sophisticated applications, the design of Systems-on-Chip (SoC) is...
HPCA
2003
IEEE
14 years 7 months ago
2003
IEEE
Java-based middleware, and application servers in particular, are rapidly gaining importance as a new class of workload for commercial multiprocessor servers. SPEC has recognized ...