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ICS
1999
Tsinghua U.
14 years 10 days ago
Realizing the performance potential of the virtual interface architecture
The Virtual Interface (VI) Architecture provides protected userlevel communication with high delivered bandwidth and low permessage latency, particularly for small messages. The V...
Evan Speight, Hazim Abdel-Shafi, John K. Bennett
CODES
2010
IEEE
13 years 6 months ago
Dynamic, non-linear cache architecture for power-sensitive mobile processors
Today, mobile smartphones are expected to be able to run the same complex, algorithm-heavy, memory-intensive applications that were originally designed and coded for generalpurpos...
Garo Bournoutian, Alex Orailoglu
DATE
2006
IEEE
115views Hardware» more  DATE 2006»
14 years 2 months ago
Optimal periodic testing of intermittent faults in embedded pipelined processor applications
Today’s nanometer technology trends have a very negative impact on the reliability of semiconductor products. Intermittent faults constitute the largest part of reliability fail...
Nektarios Kranitis, Andreas Merentitis, N. Laoutar...
WSC
1997
13 years 9 months ago
Efficient Instruction Cache Simulation and Execution Profiling with a Threaded-Code Interpreter
We present an extension to an existing SPARC V8 instruction set simulator, SimICS, to support accurate profiling of branches and instruction cache misses. SimICS had previously su...
Peter S. Magnusson
HICSS
2009
IEEE
106views Biometrics» more  HICSS 2009»
14 years 2 months ago
A Radical Approach to Network-on-Chip Operating Systems
Operating systems were created to provide multiple tasks with access to scarce hardware resources like CPU, memory, or storage. Modern programmable hardware, however, may contain ...
Michael Engel, Olaf Spinczyk