202 search results - page 19 / 41 » The Instruction Execution Mechanism for Responsive Multithre... |
ISCA
2008
IEEE
14 years 3 months ago
2008
IEEE
The current trend is for processors to deliver dramatic improvements in parallel performance while only modestly improving serial performance. Parallel performance is harvested th...
ICS
2004
Tsinghua U.
14 years 2 months ago
2004
Tsinghua U.
In contemporary out-of-order superscalar design, high IPC is mainly achieved by exposing high instruction level parallelism (ILP). Scaling issue window size can certainly provide ...
CASES
2008
ACM
13 years 10 months ago
2008
ACM
While technology advances have made MPSoCs a standard architecture for embedded systems, their applicability is increasingly being challenged by dramatic increases in the amount o...
TDSC
2010
13 years 3 months ago
2010
We describe Instruction-Set Randomization (ISR), a general approach for safeguarding systems against any type of code-injection attack. We apply Kerckhoffs' principle to creat...
ASPDAC
2000
ACM
14 years 10 days ago
2000
ACM
The paper presents an application specific Java processor including reconfigurabilities, which is a DLX like pipeline processor with 5 stages and executes Java byte codes directly....