202 search results - page 31 / 41 » The Instruction Execution Mechanism for Responsive Multithre... |
DATE
2009
IEEE
14 years 2 months ago
2009
IEEE
This paper presents a novel technique for the modeling, simulation, and analysis of real-time applications on MultiProcessor Systems-on-Chip (MPSoCs). This technique is based on a...
MICRO
1995
IEEE
13 years 11 months ago
1995
IEEE
Untolerated load instruction latencies often have a significant impact on overall program performance. As one means of mitigating this effect, we present an aggressive hardware-b...
HPCA
1999
IEEE
13 years 12 months ago
1999
IEEE
In general-purpose microprocessors, recent trends have pushed towards 64-bit word widths, primarily to accommodate the large addressing needs of some programs. Many integer proble...
CASES
2005
ACM
13 years 9 months ago
2005
ACM
Computer security becomes increasingly important with continual growth of the number of interconnected computing platforms. Moreover, as capabilities of embedded processors increa...
IPPS
2009
IEEE
14 years 2 months ago
2009
IEEE
When investigating the performance of running scientific/ commercial workflows in parallel and distributed systems, we often take into account only the resources allocated to the ...