Sciweavers

202 search results - page 34 / 41
» The Instruction Execution Mechanism for Responsive Multithre...
Sort
View
CCS
2003
ACM
14 years 23 days ago
Countering code-injection attacks with instruction-set randomization
We describe a new, general approach for safeguarding systems against any type of code-injection attack. We apply Kerckhoff’s principle, by creating process-specific randomized ...
Gaurav S. Kc, Angelos D. Keromytis, Vassilis Preve...
IISWC
2008
IEEE
14 years 1 months ago
Energy-aware application scheduling on a heterogeneous multi-core system
Heterogeneous multi-core processors are attractive for power efficient computing because of their ability to meet varied resource requirements of diverse applications in a workloa...
Jian Chen, Lizy Kurian John
ICCD
2006
IEEE
103views Hardware» more  ICCD 2006»
14 years 4 months ago
Architectural Support for Run-Time Validation of Control Flow Transfer
—Current micro-architecture blindly uses the address in the program counter to fetch and execute instructions without validating its legitimacy. Whenever this blind-folded instru...
Yixin Shi, Sean Dempsey, Gyungho Lee
TCAD
2008
101views more  TCAD 2008»
13 years 7 months ago
Using Field-Repairable Control Logic to Correct Design Errors in Microprocessors
Functional correctness is a vital attribute of any hardware design. Unfortunately, due to extremely complex architectures, widespread components, such as microprocessors, are often...
Ilya Wagner, Valeria Bertacco, Todd M. Austin
IPPS
2005
IEEE
14 years 1 months ago
Scheduling Processor Voltage and Frequency in Server and Cluster Systems
Modern server farm and cluster sites consume large quantities of energy both to power and cool the machines in the site. At the same time, less power supply redundancy is offered ...
Ramakrishna Kotla, Soraya Ghiasi, Tom W. Keller, F...