202 search results - page 5 / 41 » The Instruction Execution Mechanism for Responsive Multithre... |
ISCAPDCS
2001
13 years 9 months ago
2001
This paper presents the evaluation of a non-blocking, decoupled memory/execution, multithreaded architecture known as the Scheduled Dataflow (SDF). The major recent trend in digit...
ISCA
1998
IEEE
13 years 11 months ago
1998
IEEE
This paper examines simultaneous multithreading, a technique permitting several independent threads to issue instructions to a superscalar's multiple functional units in a si...
ISCA
2000
IEEE
13 years 12 months ago
2000
IEEE
Smaller feature sizes, reduced voltage levels, higher transistor counts, and reduced noise margins make future generations of microprocessors increasingly prone to transient hardw...
ICPP
2008
IEEE
14 years 1 months ago
2008
IEEE
The issue queue (IQ) is a key microarchitecture structure for exploiting instruction-level and thread-level parallelism in dynamically scheduled simultaneous multithreaded (SMT) p...
HIPEAC
2009
Springer
14 years 2 months ago
2009
Springer
Abstract. Threads experiencing long-latency loads on a simultaneous multithreading (SMT) processor may clog shared processor resources without making forward progress, thereby star...