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INFOCOM
1999
IEEE
14 years 2 months ago
An Architecture for Noncooperative QoS Provision in Many-Switch Systems
With the proliferation of high-speed networks and networked services, provisioning differentiated services to a diverse user base with heterogeneous QoS requirements has become an ...
Shaogang Chen, Kihong Park
VLSID
2008
IEEE
142views VLSI» more  VLSID 2008»
14 years 4 months ago
Incorporating PVT Variations in System-Level Power Exploration of On-Chip Communication Architectures
With the shift towards deep sub-micron (DSM) technologies, the increase in leakage power and the adoption of poweraware design methodologies have resulted in potentially significa...
Sudeep Pasricha, Young-Hwan Park, Fadi J. Kurdahi,...
ISMAR
2007
IEEE
14 years 4 months ago
A System Architecture for Ubiquitous Tracking Environments
Ubiquitous tracking setups, covering large tracking areas with many heterogeneous sensors of varying accuracy, require dedicated middleware to facilitate development of stationary...
Manuel Huber, Daniel Pustka, Peter Keitler, Floria...
JCDL
2003
ACM
221views Education» more  JCDL 2003»
14 years 3 months ago
The Interactive Shared Educational Environment: User Interface, System Architecture and Field Study
The user interface and system architecture of a novel Interactive Shared Educational Environment (ISEE) are presented. Based on a lightweight infrastructure, ISEE enables relative...
Xiangming Mu, Gary Marchionini, Amy Pattee
HPCC
2009
Springer
14 years 2 months ago
A Quantitative Study of Memory System Interference in Chip Multiprocessor Architectures
—The potential for destructive interference between running processes is increased as Chip Multiprocessors (CMPs) share more on-chip resources. We believe that understanding the ...
Magnus Jahre, Marius Grannæs, Lasse Natvig