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TVLSI
2010
13 years 4 months ago
LOPASS: A Low-Power Architectural Synthesis System for FPGAs With Interconnect Estimation and Optimization
In this paper, we present a low-power architectural synthesis system (LOPASS) for field-programmable gate-array (FPGA) designs with interconnect power estimation and optimization. ...
Deming Chen, Jason Cong, Yiping Fan, Lu Wan
VTC
2007
IEEE
133views Communications» more  VTC 2007»
14 years 4 months ago
An Architecture for Situation-Aware Driver Assistance Systems
Current Driver Assistance Systems merely use a minimum set of information. By using additional information of the environment hazardous situations can be detected earlier, more re...
Matthias Röckl, Patrick Robertson, Korbinian ...
MSS
2005
IEEE
175views Hardware» more  MSS 2005»
14 years 3 months ago
High Performance Storage System Scalability: Architecture, Implementation and Experience
The High Performance Storage System (HPSS) provides scalable hierarchical storage management (HSM), archive, and file system services. Its design, implementation and current domin...
Richard W. Watson
DFT
2003
IEEE
64views VLSI» more  DFT 2003»
14 years 3 months ago
Hybrid BIST Time Minimization for Core-Based Systems with STUMPS Architecture
1 This paper presents a solution to the test time minimization problem for core-based systems that contain sequential cores with STUMPS architecture. We assume a hybrid BIST approa...
Gert Jervan, Petru Eles, Zebo Peng, Raimund Ubar, ...
ICSM
1997
IEEE
14 years 2 months ago
Dynamic Traceability Links Supported by a System Architecture Description
To reduce the effort spent on system comprehension during software maintenance, easy access to different type of information describing the system features is necessary. This is u...
Eirik Tryggeseth, Øystein Nytrø