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MEMOCODE
2005
IEEE
14 years 2 months ago
Three-valued logic in bounded model checking
In principle, bounded model checking (BMC) leads to semidecision procedures that can be used to verify liveness properties and to falsify safety properties. If the procedures fail...
Tobias Schüle, Klaus Schneider
PATMOS
2005
Springer
14 years 2 months ago
A New Model for Timing Jitter Caused by Device Noise in Current-Mode Logic Frequency Dividers
A new method for predicting timing jitter caused by device noise in current-mode logic (CML) frequency dividers is presented. Device noise transformation into jitter is modeled as ...
Marko Aleksic, Nikola Nedovic, K. Wayne Current, V...
DAC
1994
ACM
14 years 1 months ago
Statistical Delay Modeling in Logic Design and Synthesis
Manufacturing disturbances are inevitable in the fabrication of integrated circuits. These disturbances will result in variations in the delay speci cations of manufactured circui...
Horng-Fei Jyu, Sharad Malik
SIP
2007
13 years 10 months ago
Occlusion tracking using logic models
We present a variational PDE based model for tracking objects under occlusion. Here, prior shape information is used to segment object boundaries that are occluded. The novelty in...
J. H. von Brecht, Sheshadri R. Thiruvenkadam, Tony...
DALT
2004
Springer
14 years 29 days ago
Modeling and Verification of Distributed Autonomous Agents Using Logic Programming
Systems of autonomous agents providing automated services over the Web are fast becoming a reality. Often these agent systems are constructed using procedural architectures that pr...
L. Robert Pokorny, C. R. Ramakrishnan