41 search results - page 7 / 9 » The Latency Hiding Effectiveness of Decoupled Access Execute... |
ARCS
2009
Springer
14 years 1 months ago
2009
Springer
The disparity between microprocessor clock frequencies and memory latency is a primary reason why many demanding applications run well below peak achievable performance. Software c...
COMPUTING
2004
13 years 7 months ago
2004
The presented image registration method uses a regularized gradient flow to correlate the intensities in two images. Thereby, an energy functional is successively minimized by des...
ISCA
2002
IEEE
14 years 8 days ago
2002
IEEE
Many emerging processor microarchitectures seek to manage technological constraints (e.g., wire delay, power, and circuit complexity) by resorting to nonuniform designs that provi...
ICCD
2007
IEEE
14 years 4 months ago
2007
IEEE
This paper presents the Finished Store Buffer (or FSB), an alternative and position-insensitive approach for building a scalable store buffer for an out-of-order processor. Exploi...
EUROPAR
2000
Springer
13 years 11 months ago
2000
Springer
Abstract This paper examines the behavior of current and next generation microprocessors' fetch engines while running Decision Support Systems (DSS) workloads. We analyze the ...