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CADE
2009
Springer
16 years 4 months ago
Solving Non-linear Polynomial Arithmetic via SAT Modulo Linear Arithmetic
Abstract. Polynomial constraint-solving plays a prominent role in several areas of engineering and software verification. In particular, polynomial constraint solving has a long an...
Albert Rubio, Cristina Borralleras, Enric Rodr&iac...
DATE
2008
IEEE
143views Hardware» more  DATE 2008»
15 years 10 months ago
Improving Synthesis of Compressor Trees on FPGAs via Integer Linear Programming
Multi-input addition is an important operation for many DSP and video processing applications. On FPGAs, multi-input addition has traditionally been implemented using trees of car...
Hadi Parandeh-Afshar, Philip Brisk, Paolo Ienne
129
Voted
APLAS
2004
ACM
15 years 9 months ago
Translation of Tree-Processing Programs into Stream-Processing Programs Based on Ordered Linear Type
There are two ways to write a program for manipulating tree-structured data such as XML documents: One is to write a tree-processing program focusing on the logical structure of t...
Koichi Kodama, Kohei Suenaga, Naoki Kobayashi
118
Voted
CONCUR
1998
Springer
15 years 7 months ago
It's About Time: Real-Time Logics Reviewed
Abstract. We summarize and reorganize some of the last decade's research on real-time extensions of temporal logic. Our main focus is on tableau constructions for model checki...
Thomas A. Henzinger
132
Voted
FPGA
2008
ACM
145views FPGA» more  FPGA 2008»
15 years 5 months ago
FPGA interconnect design using logical effort
Logical effort (LE) is a linear technique for modelling the delay of a circuit in a technology independent manner. It offers the potential to simplify delay models for FPGAs and g...
Haile Yu, Yuk Hei Chan, Philip Heng Wai Leong