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» The Logic of Correctness in Software Engineering
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DAC
2002
ACM
16 years 7 months ago
High-Level specification and automatic generation of IP interface monitors
A central problem in functional verification is to check that a circuit block is producing correct outputs while enforcing that the environment is providing legal inputs. To attac...
Marcio T. Oliveira, Alan J. Hu
DFG
2004
Springer
15 years 11 months ago
Combining Formal Methods and Safety Analysis - The ForMoSA Approach
In the ForMoSA project [17] an integrated approach for safety analysis of critical, embedded systems has been developed. The approach brings together the best of engineering practi...
Frank Ortmeier, Andreas Thums, Gerhard Schellhorn,...
PADS
2003
ACM
15 years 11 months ago
DVS: An Object-Oriented Framework for Distributed Verilog Simulation
There is a wide-spread usage of hardware design languages(HDL) to speed up the time-to-market for the design of modern digital systems. Verification engineers can simulate hardwa...
Lijun Li, Hai Huang, Carl Tropper
FM
2003
Springer
109views Formal Methods» more  FM 2003»
15 years 11 months ago
Certifying and Synthesizing Membership Equational Proofs
As the systems we have to specify and verify become larger and more complex, there is a mounting need to combine different tools and decision procedures to accomplish large proof ...
Grigore Rosu, Steven Eker, Patrick Lincoln, Jos&ea...
SEKE
2007
Springer
16 years 9 days ago
Managing XML Versions and Replicas in a P2P Context
Peer-to-Peer (P2P) systems seek to provide sharing of computational resources, which may be duplicated or versioned over several peers. Duplicate resources (i.e. replicas) are the...
Deise de Brum Saccol, Nina Edelweiss, Renata de Ma...