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» The Logic of Large Enough
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TVLSI
2002
93views more  TVLSI 2002»
13 years 9 months ago
Simultaneous switching noise in on-chip CMOS power distribution networks
Simultaneous switching noise (SSN) has become an important issue in the design of the internal on-chip power distribution networks in current very large scale integration/ultra lar...
Kevin T. Tang, Eby G. Friedman
ENTCS
2007
158views more  ENTCS 2007»
13 years 9 months ago
Abstraction and Completeness for Real-Time Maude
ion and Completeness for Real-Time Maude Peter Csaba ¨Olveczky a,b and Jos´e Meseguer b a Department of Informatics, University of Oslo b Department of Computer Science, Universi...
Peter Csaba Ölveczky, José Meseguer
DATE
2006
IEEE
158views Hardware» more  DATE 2006»
14 years 3 months ago
Modeling multiple input switching of CMOS gates in DSM technology using HDMR
Abstract— Continuing scaling of CMOS technology has allowed aggressive pursuant of increased clock rate in DSM chips. The ever shorter clock period has made switching times of di...
Jayashree Sridharan, Tom Chen
OTM
2005
Springer
14 years 2 months ago
Spatio-temporal Schema Integration with Validation: A Practical Approach
We propose to enhance a schema integration process with a validation phase employing logic-based data models. In our methodology, we validate the source schemas against the data mo...
Anastasiya Sotnykova, Nadine Cullot, Christelle Va...
EVOW
2001
Springer
14 years 1 months ago
ARPIA: A High-Level Evolutionary Test Signal Generator
The integrated circuits design flow is rapidly moving towards higher description levels. However, test-related activities are lacking behind this trend, mainly since effective faul...
Fulvio Corno, Gianluca Cumani, Matteo Sonza Reorda...