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» The Logic of Large Enough
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DATE
2005
IEEE
158views Hardware» more  DATE 2005»
14 years 1 months ago
Modeling and Analysis of Loading Effect in Leakage of Nano-Scaled Bulk-CMOS Logic Circuits
In nanometer scaled CMOS devices significant increase in the subthreshold, the gate and the reverse biased junction band-toband-tunneling (BTBT) leakage, results in the large incr...
Saibal Mukhopadhyay, Swarup Bhunia, Kaushik Roy
ICLP
1998
Springer
13 years 12 months ago
Efficient Implementation of a Linear Logic Programming Language
A number of logic programming languages based on Linear Logic [3] have been proposed. However, the implementation techniques proposed for these languages have relied heavily on th...
Joshua S. Hodas, K. M. Watkins, Naoyuki Tamura, Ky...
TACAS
2007
Springer
116views Algorithms» more  TACAS 2007»
14 years 1 months ago
Model Checking on Trees with Path Equivalences
For specifying and verifying branching-time requirements, a reactive system is traditionally modeled as a labeled tree, where a path in the tree encodes a possible execution of the...
Rajeev Alur, Pavol Cerný, Swarat Chaudhuri
DATE
2002
IEEE
83views Hardware» more  DATE 2002»
14 years 22 days ago
Reconfigurable SoC - What Will it Look Like?
The argument against ASIC SoCs is that they have always taken too long and cost too much to design. As new process technologies come on line, the issue of inflexible, unyielding d...
J. Bryan Lewis, Ivo Bolsens, Rudy Lauwereins, Chri...
DATE
2002
IEEE
206views Hardware» more  DATE 2002»
14 years 22 days ago
Accurate Area and Delay Estimators for FPGAs
We present an area and delay estimator in the context of a compiler that takes in high level signal and image processing applications described in MATLAB and performs automatic de...
Anshuman Nayak, Malay Haldar, Alok N. Choudhary, P...