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RSP
2005
IEEE
155views Control Systems» more  RSP 2005»
14 years 1 months ago
Optimization Techniques for ADL-Driven RTL Processor Synthesis
Nowadays, Architecture Description Languages (ADLs) are getting popular to speed up the development of complex SoC design, by performing the design space explon a higher level of ...
Oliver Schliebusch, Anupam Chattopadhyay, Ernst Ma...
LCPC
2004
Springer
14 years 1 months ago
Power-Aware Scheduling for Parallel Security Processors with Analytical Models
Techniques to reduce power dissipation for embedded systems have recently come into sharp focus in the technology development. Among these techniques, dynamic voltage scaling (DVS)...
Yung-Chia Lin, Yi-Ping You, Chung-Wen Huang, Jenq ...
ERSA
2008
130views Hardware» more  ERSA 2008»
13 years 9 months ago
Evaluation of MuCCRA-D: A Dynamically Reconfigurable Processor with Directly Interconnected PEs
Coarse-grained dynamically reconfigurable processor arrays (DRPAs) have been received an attention as a flexible and efficient off-loading engine for various types of System-on-Ch...
Masaru Kato, Yohei Hasegawa, Hideharu Amano
ANCS
2008
ACM
13 years 9 months ago
On runtime management in multi-core packet processing systems
Computer networks require increasingly complex packet processing in the data path to adapt to new functionality requirements. To meet performance demands, packet processing system...
Qiang Wu, Tilman Wolf
DATE
2003
IEEE
104views Hardware» more  DATE 2003»
14 years 29 days ago
Efficient Field Processing Cores in an Innovative Protocol Processor System-on-Chip
We present an innovative protocol processor component that combines wire-speed processing for low-level, and best effort processing for higher-level protocols. The component is a ...
George Lykakis, N. Mouratidis, Kyriakos Vlachos, N...