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FPGA
2010
ACM
209views FPGA» more  FPGA 2010»
14 years 4 months ago
FPGA power reduction by guarded evaluation
Guarded evaluation is a power reduction technique that involves identifying sub-circuits (within a larger circuit) whose inputs can be held constant (guarded) at specific times d...
Chirag Ravishankar, Jason Helge Anderson
COMSWARE
2007
IEEE
14 years 1 months ago
OASiS: A Programming Framework for Service-Oriented Sensor Networks
Abstract— Wireless sensor networks consist of small, inexpensive devices which interact with the environment, communicate with each other, and perform distributed computations in...
Manish Kushwaha, Isaac Amundson, Xenofon D. Koutso...
CIKM
2007
Springer
14 years 1 months ago
Ontology module extraction for ontology reuse: an ontology engineering perspective
Problems resulting from the management of shared, distributed knowledge has led to ontologies being employed as a solution, in order to effectively integrate information across a...
Paul Doran, Valentina A. M. Tamma, Luigi Iannone
VISUALIZATION
2005
IEEE
14 years 1 months ago
Topology-driven Surface Mappings with Robust Feature Alignment
Topological concepts and techniques have been broadly applied in computer graphics and geometric modeling. However, the homotopy type of a mapping between two surfaces has not bee...
Christopher Carner, Miao Jin, Xianfeng Gu, Hong Qi...
SSS
2005
Springer
14 years 28 days ago
Synchronous vs. Asynchronous Unison
This paper considers the self-stabilizing unison problem. The contribution of this paper is threefold. First, we establish that when any self-stabilizing asynchronous unison protoc...
Christian Boulinier, Franck Petit, Vincent Villain