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» The Modal Logic of Probability
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FORMATS
2003
Springer
14 years 4 months ago
Performance Analysis of Probabilistic Timed Automata Using Digital Clocks
Probabilistic timed automata, a variant of timed automata extended with discrete probability distributions, is a specification formalism suitable for describing both nondeterminis...
Marta Z. Kwiatkowska, Gethin Norman, David Parker,...
VTS
2002
IEEE
120views Hardware» more  VTS 2002»
14 years 3 months ago
Software-Based Weighted Random Testing for IP Cores in Bus-Based Programmable SoCs
We present a software-based weighted random pattern scheme for testing delay faults in IP cores of programmable SoCs. We describe a method for determining static and transition pr...
Madhu K. Iyer, Kwang-Ting Cheng
ITC
1998
IEEE
114views Hardware» more  ITC 1998»
14 years 3 months ago
BETSY: synthesizing circuits for a specified BIST environment
This paper presents a logic synthesis tool called BETSY (BIST Environment Testable Synthesis) for synthesizing circuits that achieve complete (100%)fault coverage in a user specif...
Zhe Zhao, Bahram Pouya, Nur A. Touba
DSD
2007
IEEE
132views Hardware» more  DSD 2007»
14 years 2 months ago
On-Chip Cache Device Scaling Limits and Effective Fault Repair Techniques in Future Nanoscale Technology
In this study, we investigate different cache fault tolerance techniques to determine which will be most effective when on-chip memory cell defect probabilities exceed those of cu...
David Roberts, Nam Sung Kim, Trevor N. Mudge
DEBS
2010
ACM
14 years 2 months ago
Predictive publish/subscribe matching
A new publish/subscribe capability is presented: the ability to predict the likelihood that a subscription will be matched at some point in the future. Composite subscriptions con...
Vinod Muthusamy, Haifeng Liu, Hans-Arno Jacobsen