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VLSI
2005
Springer
15 years 8 months ago
Combined Test Data Selection and Scheduling for Test Quality Optimization under ATE Memory Depth Constraint
1 The increasing test data volume required to ensure high test quality when testing a System-on-Chip is becoming a problem since it (the test data volume) must fit the ATE (Automa...
Erik Larsson, Stina Edbom
VLSI
2005
Springer
15 years 8 months ago
Pareto Points in SRAM Design Using the Sleepy Stack Approach
Leakage power consumption of current CMOS technology is already a great challenge. ITRS projects that leakage power consumption may come to dominate total chip power consumption a...
Jun-Cheol Park, Vincent John Mooney III
VLSI
2005
Springer
15 years 8 months ago
Modeling the Traffic Effect for the Application Cores Mapping Problem onto NoCs
This work addresses the problem of application mapping in networks-on-chip (NoCs) having as goal to minimize the total dynamic energy consumption of a complex system-on-a-chip (So...
César A. M. Marcon, José Carlos S. P...
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ARCS
2005
Springer
15 years 8 months ago
Reusable Design of Inter-chip Communication Interfaces for Next Generation of Adaptive Computing Systems
Abstract. The SoC (System-on-Chip) technology is used in small and flexible consumer electronic devices. SoCs include one or more microcontroller, memory, programmable logic, and ...
Vincent Kotzsch, Jörg Schneider, Günther...
ACMMSP
2004
ACM
101views Hardware» more  ACMMSP 2004»
15 years 8 months ago
Metrics and models for reordering transformations
Irregular applications frequently exhibit poor performance on contemporary computer architectures, in large part because of their inefficient use of the memory hierarchy. Runtime ...
Michelle Mills Strout, Paul D. Hovland
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