314 search results - page 10 / 63 » The Nachos Instructional Operating System |
ASPLOS
2006
ACM
14 years 1 months ago
2006
ACM
While hardware instruction caches are present in virtually all general-purpose and high-performance microprocessors today, many embedded processors use SRAM or scratchpad memories...
CASES
2000
ACM
13 years 11 months ago
2000
ACM
This paper introduces the notion of a Flexible Instruction Processor (FIP) for systematic customisation of instruction processor design and implementation. The features of our app...
WSC
1997
13 years 9 months ago
1997
We present an extension to an existing SPARC V8 instruction set simulator, SimICS, to support accurate profiling of branches and instruction cache misses. SimICS had previously su...
IPPS
2006
IEEE
14 years 1 months ago
2006
IEEE
We present a novel technique to secure the execution of a processor against the execution of malicious code (trojans, viruses). The main idea is to permute parts of the opcode val...
ICCD
2004
IEEE
14 years 4 months ago
2004
IEEE
As the performance gap between processors and memory systems increases, the CPU spends more time stalled waiting for data from main memory. Critical long latency instructions, suc...