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» The Observational Power of Clocks
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TCAD
2011
13 years 2 months ago
Low-Power Clock Tree Design for Pre-Bond Testing of 3-D Stacked ICs
—Pre-bond testing of 3-D stacked integrated circuits (ICs) involves testing each individual die before bonding. The overall yield of 3-D ICs improves with pre-bond testability be...
Xin Zhao, Dean L. Lewis, Hsien-Hsin S. Lee, Sung K...
VLSID
2005
IEEE
82views VLSI» more  VLSID 2005»
14 years 7 months ago
Dual-Edge Triggered Static Pulsed Flip-Flops
Two Simple structures of low-power Dual-edge triggered Static Pulsed Flip-Flops (DSPFF) are presented in this paper. They are composed of a dualedge pulse generator and a static f...
Aliakbar Ghadiri, Hamid Mahmoodi-Meimand
DATE
2009
IEEE
129views Hardware» more  DATE 2009»
14 years 2 months ago
Multi-domain clock skew scheduling-aware register placement to optimize clock distribution network
Multi-domain clock skew scheduling is a cost effective technique for performance improvement. However, the required wire length and area overhead due to phase shifters for realizin...
Naser MohammadZadeh, Minoo Mirsaeedi, Ali Jahanian...
TVLSI
2002
79views more  TVLSI 2002»
13 years 7 months ago
Electrical and optical clock distribution networks for gigascale microprocessors
A summary of electrical and optical approaches to clock distribution within high-performance microprocessors is presented. System-level properties of intrachip electrical clock dis...
A. V. Mule, Elias N. Glytsis, Thomas K. Gaylord, J...
INTERACT
2007
13 years 8 months ago
MarkerClock: A Communicating Augmented Clock for Elderly
Abstract. This paper presents markerClock, a communication appliance embedded into a clock and designed for seniors as a simple and intuitive device. MarkerClock enhances seniorsâ€...
Yann Riche, Wendy E. Mackay