Sciweavers

1542 search results - page 9 / 309
» The Observational Power of Clocks
Sort
View
ASPDAC
2007
ACM
87views Hardware» more  ASPDAC 2007»
13 years 11 months ago
An Embedded Low Power/Cost 16-Bit Data/Instruction Microprocessor Compatible with ARM7 Software Tools
- A 16-bit THUMB instruction set microprocessor is proposed for low cost/power in short-precision computing. It achieves 40% gate count, 51% power consumption and 160% clock freque...
Fu-Ching Yang, Ing-Jer Huang
ISVLSI
2006
IEEE
88views VLSI» more  ISVLSI 2006»
14 years 1 months ago
Effects of Parameter Variations and Crosstalk Noise on H-Tree Clock Distribution Networks
— The effects of parameter variations and crosstalk noise on the clock signal propagating along an H-tree clock distribution network are investigated in this paper. In particular...
Itisha Chanodia, Dimitrios Velenis
ISVLSI
2007
IEEE
232views VLSI» more  ISVLSI 2007»
14 years 1 months ago
DSPstone Benchmark of CoDeL's Automated Clock Gating Platform
— We present a performance analysis of CoDeL, a highly efficient automated clock gating platform for rapidly developing power efficient hardware architectures. It automatically...
Nainesh Agarwal, Nikitas J. Dimopoulos
ASPDAC
2005
ACM
90views Hardware» more  ASPDAC 2005»
13 years 9 months ago
Register placement for low power clock network
In modern VLSI designs, the increasingly severe power problem requests to minimize clock routing wirelength so that both power consumption and power supply noise can be alleviated...
Yongqiang Lu, Cliff C. N. Sze, Xianlong Hong, Qian...
VTS
2008
IEEE
78views Hardware» more  VTS 2008»
14 years 1 months ago
Expanding Trace Buffer Observation Window for In-System Silicon Debug through Selective Capture
Trace buffers are commonly used to capture data during in-system silicon debug. This paper exploits the fact that it is not necessary to capture error-free data in the trace buffe...
Joon-Sung Yang, Nur A. Touba