In this paper we report the fully depleted CMOS/SOI device design guidelines for low power applications. Optimal technology, device and circuit parameters are discussed and compar...
Srinivasa R. Banna, Philip C. H. Chan, Mansun Chan...
In this paper, capacitive 4-PWAM transmitter architectures and circuits are proposed and its performances are analyzed with random jitter and PVT variation comparing with other wo...
- A 16-bit THUMB instruction set microprocessor is proposed for low cost/power in short-precision computing. It achieves 40% gate count, 51% power consumption and 160% clock freque...
—This paper provides a power-margin-based measure of the quality of computer-generated random variates having a distribution that derives from the multivariate Gaussian distribut...
A 30 W LDMOS is modeled using a 5th order polynomial model. The polynomial model is compared to the largesignal MET model using harmonic balance, and as the results agreed very we...