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ISLPED
1997
ACM
91views Hardware» more  ISLPED 1997»
14 years 14 days ago
Fully depleted CMOS/SOI device design guidelines for low power applications
In this paper we report the fully depleted CMOS/SOI device design guidelines for low power applications. Optimal technology, device and circuit parameters are discussed and compar...
Srinivasa R. Banna, Philip C. H. Chan, Mansun Chan...
GLVLSI
2010
IEEE
189views VLSI» more  GLVLSI 2010»
14 years 2 months ago
8Gb/s capacitive low power and high speed 4-PWAM transceiver design
In this paper, capacitive 4-PWAM transmitter architectures and circuits are proposed and its performances are analyzed with random jitter and PVT variation comparing with other wo...
Young Bok Kim, Yong-Bin Kim, Fabrizio Lombardi
ASPDAC
2007
ACM
87views Hardware» more  ASPDAC 2007»
14 years 28 days ago
An Embedded Low Power/Cost 16-Bit Data/Instruction Microprocessor Compatible with ARM7 Software Tools
- A 16-bit THUMB instruction set microprocessor is proposed for low cost/power in short-precision computing. It achieves 40% gate count, 51% power consumption and 160% clock freque...
Fu-Ching Yang, Ing-Jer Huang
ICC
2007
IEEE
14 years 3 months ago
A Simple Power Margin Quality Measure for Correlated Random Variates Derived from the Normal Distribution
—This paper provides a power-margin-based measure of the quality of computer-generated random variates having a distribution that derives from the multivariate Gaussian distribut...
David J. Young, Norman C. Beaulieu
ISCAS
2003
IEEE
101views Hardware» more  ISCAS 2003»
14 years 2 months ago
A 5th order Volterra study of a 30W LDMOS power amplifier
A 30 W LDMOS is modeled using a 5th order polynomial model. The polynomial model is compared to the largesignal MET model using harmonic balance, and as the results agreed very we...
Antti Heiskanen, Janne Aikio, Timo Rahkonen