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» The Power of Hybrid Acceleration
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ISSS
2002
IEEE
174views Hardware» more  ISSS 2002»
14 years 19 days ago
A Run-Time Word-Level Reconfigurable Coarse-Grain Functional Unit for a VLIW Processor
Nowadays, new DSP applications are offering combined and flexible multimedia and telecom services. VLIW processor architectures, which include dedicated but inflexible functional ...
Carles Rodoreda Sala, Natalino G. Busá
SEAL
1998
Springer
13 years 12 months ago
Genetic Programming with Active Data Selection
Genetic programming evolves Lisp-like programs rather than fixed size linear strings. This representational power combined with generality makes genetic programming an interesting ...
Byoung-Tak Zhang, Dong-Yeon Cho
DSN
2009
IEEE
13 years 11 months ago
Processor reliability enhancement through compiler-directed register file peak temperature reduction
Each semiconductor technology generation brings us closer to the imminent processor architecture heat wall, with all its associated adverse effects on system performance and reliab...
Chengmo Yang, Alex Orailoglu
CSB
2004
IEEE
108views Bioinformatics» more  CSB 2004»
13 years 11 months ago
Embedded Computation of Maximum-Likelihood Phylogeny Inference Using Platform FPGA
Our previous work to accelerate phylogeny inference using HW/SW(Hardware/Software) co-design has recently been extended to a more powerful embedded computing platform. In this pla...
Terrence S. T. Mak, Kai-Pui Lam
FPL
2004
Springer
119views Hardware» more  FPL 2004»
13 years 11 months ago
Reconfigurable Instruction Set Extension for Enabling ECC on an 8-Bit Processor
Pervasive networks with low-cost embedded 8-bit processors are set to change our day-to-day life. Public-key cryptography provides crucial functionality to assure security which is...
Sandeep S. Kumar, Christof Paar