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» The Power of Hybrid Acceleration
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IPPS
2005
IEEE
14 years 2 months ago
Analysis of Hardware Acceleration in Reconfigurable Embedded Systems
Embedded designers now have the capability of offloading software routines into custom applicationspecific hardware blocks. This paper evaluates a domain-specific design system fo...
Matthew Ouellette, Daniel A. Connors
IBPRIA
2005
Springer
14 years 2 months ago
Hardware-Accelerated Template Matching
In the last decade, consumer graphics cards have increased their power because of the computer games industry. These cards are now programmable and capable of processing huge amoun...
Raúl Cabido, Antonio S. Montemayor, Á...
ISSPIT
2010
13 years 3 months ago
Accelerating the Nussinov RNA folding algorithm with CUDA/GPU
Graphics processing units (GPU) on commodity video cards have evolved into powerful computational devices. The RNA secondary structure arises from the primary structure and a backb...
Dar-Jen Chang, Christopher Kimmer, Ming Ouyang
ICML
2007
IEEE
14 years 9 months ago
Best of both: a hybridized centroid-medoid clustering heuristic
Although each iteration of the popular kMeans clustering heuristic scales well to larger problem sizes, it often requires an unacceptably-high number of iterations to converge to ...
Nizar Grira, Michael E. Houle
DAC
2008
ACM
14 years 9 months ago
DVFS in loop accelerators using BLADES
Hardware accelerators are common in embedded systems that have high performance requirements but must still operate within stringent energy constraints. To facilitate short time-t...
Ganesh S. Dasika, Shidhartha Das, Kevin Fan, Scott...