782 search results - page 41 / 157 » The Power of Hybrid Acceleration |
CSE
2011
IEEE
12 years 8 months ago
2011
IEEE
In this paper, we present a performance modeling framework based on memory bandwidth contention time and a parameterized communication model to predict the performance of OpenMP, M...
ICCD
2002
IEEE
14 years 5 months ago
2002
IEEE
Dynamically-loaded tagless loop caching reduces instruction fetch power for embedded software with small loops, but only supports simple loops without taken branches. Preloaded ta...
CORR
2008
Springer
13 years 9 months ago
2008
Springer
Position control devices enable precise selection, but significant clutching degrades performance. Clutching can be reduced with high control-display gain or pointer acceleration,...
ICCAD
2009
IEEE
13 years 6 months ago
2009
IEEE
Hardware acceleration is crucial in modern embedded system design to meet the explosive demands on performance and cost. Selected computation kernels for acceleration are usually ...
CIKM
2003
Springer
14 years 2 months ago
2003
Springer
Hybrid peer-to-peer architectures use special nodes to provide directory services for regions of the network (“regional directory services”). Hybrid peer-to-peer architectures...