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» The Power of Hybrid Acceleration
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IPPS
2006
IEEE
14 years 3 months ago
Architecture of a multi-context FPGA using a hybrid multiple-valued/binary context switching signal
Multi-context FPGAs have multiple memory bits per configuration bit forming configuration planes for fast switching between contexts. Large amount of memory causes significant ove...
Yoshihiro Nakatani, Masanori Hariyama, Michitaka K...
DATE
2010
IEEE
183views Hardware» more  DATE 2010»
14 years 2 months ago
Monolithically stackable hybrid FPGA
— The paper introduces novel field programmable gate array (FPGA) circuits based on hybrid CMOS/resistive switching device (memristor) technology and explores several logic archi...
Dmitri Strukov, Alan Mishchenko
ASAP
2000
IEEE
184views Hardware» more  ASAP 2000»
14 years 1 months ago
Tradeoff Analysis and Architecture Design of a Hybrid Hardware/Software Sorter
Sorting long sequences of keys is a problem that occurs in many different applications. For embedded systems, a uniprocessor software solution is often not applicable due to the l...
Marcus Bednara, Oliver Beyer, Jürgen Teich, R...
RTCSA
1997
IEEE
14 years 1 months ago
Behavior verification of hybrid real-time requirements by qualitative formalism
Although modern control theories have been successfully applied to solve a variety of problems, they are often mathematically and physically too specific to describe and analyze t...
Jang-Soo Lee, Sung Deok Cha
CATA
2003
13 years 10 months ago
Efficient Power-aware Hybrid Routing using Zoning for Ad Hoc Network
A number of routing protocols have been proposed for mobile ad hoc networks. In this paper we propose a hybrid multiple zoning scheme minimizing the number of route request messag...
Jong Ho Lee, Hee Yong Youn, Chansu Yu, Dongman Lee