Sciweavers

215 search results - page 31 / 43
» The Power of Quantum Systems on a Line
Sort
View
WCET
2010
13 years 5 months ago
WCET Analysis of a Parallel 3D Multigrid Solver Executed on the MERASA Multi-Core
To meet performance requirements as well as constraints on cost and power consumption, future embedded systems will be designed with multi-core processors. However, the question o...
Christine Rochange, Armelle Bonenfant, Pascal Sain...
SIGSOFT
2004
ACM
14 years 1 months ago
Resolving uncertainties during trace analysis
Software models provide independent perspectives onto software systems. Ideally, all models should use the same model element to describe the same part of a system. Practically, m...
Alexander Egyed
MICRO
2010
IEEE
156views Hardware» more  MICRO 2010»
13 years 6 months ago
Explicit Communication and Synchronization in SARC
SARC merges cache controller and network interface functions by relying on a single hardware primitive: each access checks the tag and the state of the addressed line for possible...
Manolis Katevenis, Vassilis Papaefstathiou, Stamat...
GLVLSI
2008
IEEE
140views VLSI» more  GLVLSI 2008»
14 years 2 months ago
A table-based method for single-pass cache optimization
Due to the large contribution of the memory subsystem to total system power, the memory subsystem is highly amenable to customization for reduced power/energy and/or improved perf...
Pablo Viana, Ann Gordon-Ross, Edna Barros, Frank V...
MICRO
2008
IEEE
111views Hardware» more  MICRO 2008»
14 years 2 months ago
Reducing the harmful effects of last-level cache polluters with an OS-level, software-only pollute buffer
It is well recognized that LRU cache-line replacement can be ineffective for applications with large working sets or non-localized memory access patterns. Specifically, in lastle...
Livio Soares, David K. Tam, Michael Stumm