This paper studies multi-core clock distribution using active deskewing methods. We propose an efficient methodology that uses Verilog-A to model PLLs, clock trees and power suppl...
The power dissipated by system-level buses is the largest contribution to the global power of complex VLSI circuits. Therefore, the minimization of the switching activity at the I...
Luca Benini, Giovanni De Micheli, Donatella Sciuto...
Load forecasting has become in recent years one of the major areas of research in electrical engineering. In a deregulated, competitive power market, utilities tend to maintain the...
Robert Thomas has shown, using simulations of experimental results, that the power flow on any line in an electric network is linearly proportional to the total system load when t...
Nodir Adilov, Thomas Light, Richard E. Schuler, Wi...
In xDSL systems, crosstalk can be separated into two categories, namely in-domain crosstalk and out-of-domain crosstalk. Indomain crosstalk is also refered to as self crosstalk. Ou...
Vincent Le Nir, Marc Moonen, Jan Verlinden, Mamoun...