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» The Price of Routing in FPGAs
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INFOCOM
2006
IEEE
14 years 1 months ago
Bottleneck Routing Games in Communication Networks
—We consider routing games where the performance of each user is dictated by the worst (bottleneck) element it employs. We are given a network, finitely many (selfish) users, eac...
Ron Banner, Ariel Orda
INFOCOM
2000
IEEE
13 years 12 months ago
QoS Routing with Performance-Dependent Costs
Abstract—We study a network model in which each network link is associated with a set of delays and costs. These costs are a function of the delays and reflect the prices paid i...
Funda Ergün, Rakesh K. Sinha, Lisa Zhang
DATE
2007
IEEE
150views Hardware» more  DATE 2007»
14 years 1 months ago
Assessing carbon nanotube bundle interconnect for future FPGA architectures
Field Programmable Gate Arrays (FPGAs) are important hardware platforms in various applications due to increasing design complexity and mask costs. However, as CMOS process techno...
Soumya Eachempati, Arthur Nieuwoudt, Aman Gayasen,...
FPL
2007
Springer
178views Hardware» more  FPL 2007»
14 years 1 months ago
Exploring Alternative 3D FPGA Architectures: Design Methodology and CAD Tool Support
This paper introduces a software supported methodology for exploring/evaluating 3D FPGA architectures. Two new CAD tools are developed: (i) the 3DPRO for placement and routing on ...
Kostas Siozios, Kostas Sotiriadis, Vasilis F. Pavl...
FPL
2009
Springer
113views Hardware» more  FPL 2009»
14 years 5 days ago
Static versus scheduled interconnect in Coarse-Grained Reconfigurable Arrays
Spatially-tiled architectures, such as Coarse-Grained Reconfigurable Arrays (CGRAs), are powerful architectures for accelerating applications in the digital-signal processing, em...
Brian Van Essen, Aaron Wood, Allan Carroll, Stephe...