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ISCA
2006
IEEE
123views Hardware» more  ISCA 2006»
13 years 10 months ago
A Gracefully Degrading and Energy-Efficient Modular Router Architecture for On-Chip Networks
Packet-based on-chip networks are increasingly being adopted in complex System-on-Chip (SoC) designs supporting numerous homogeneous and heterogeneous functional blocks. These Net...
Jongman Kim, Chrysostomos Nicopoulos, Dongkook Par...
SSPR
1998
Springer
14 years 2 months ago
Network-Based Recognition of Architectural Symbols
Abstract. In this paper, we propose a method for recognizing architectural symbols. The method is based on the description of the model through a set of constraints on geometrical ...
Christian Ah-Soon, Karl Tombre
IJCAI
1989
13 years 11 months ago
Beyond PDP: The Frequency Modulation Neural Network Architecture
This paper proposes the Frequency Modulation Neural Network as an alternative to current neuralnet models. This proposal is for an architecture of a heterogeneous neural-network i...
Hideto Tomabechi, Hiroaki Kitano
CCGRID
2004
IEEE
14 years 1 months ago
DWDM-RAM: a data intensive Grid service architecture enabled by dynamic optical networks
Next generation applications and architectures (for example, Grids) are driving radical changes in the nature of traffic, service models, technology, and cost, creating opportunit...
Tal Lavian, Joe Mambretti, Doug Cutrell, Howard J....
ICDCS
2007
IEEE
14 years 1 months ago
uSense: A Unified Asymmetric Sensing Coverage Architecture for Wireless Sensor Networks
As a key approach to achieve energy efficiency in sensor networks, sensing coverage has been studied extensively. Researchers have designed many coverage protocols to provide vario...
Yu Gu, Joengmin Hwang, Tian He, David Hung-Chang D...