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ICCAD
2007
IEEE
151views Hardware» more  ICCAD 2007»
14 years 2 months ago
A design flow dedicated to multi-mode architectures for DSP applications
This paper addresses the design of multi-mode architectures for digital signal processing applications. We present a dedicated design flow and its associated high-level synthesis t...
Cyrille Chavet, Caaliph Andriamisaina, Philippe Co...
ASPDAC
2004
ACM
158views Hardware» more  ASPDAC 2004»
14 years 2 months ago
Decode filter cache for energy efficient instruction cache hierarchy in super scalar architectures
Abstract-- The power consumption of microprocessors has been increasing in step with the complexity of each progressive generation. In general purpose processors, this is primarily...
Kugan Vivekanandarajah, Thambipillai Srikanthan, S...
DEXAW
2006
IEEE
164views Database» more  DEXAW 2006»
14 years 6 days ago
A P2P Integration Architecture for Protein Resources
The availability of a direct pathway from a primary sequence (denovo or DNA derived) to macromolecular structure to biological function using computer-based tools is the ultimate ...
Kajal T. Claypool, Sanjay Kumar Madria
AAAI
1997
13 years 11 months ago
Using a Robot Control Architecture to Automate Space Shuttle Operations
This paper describes preliminary results from using an AI robot control software architecture, known as 3T, as the software framework for a procedure tracking system for the space...
R. Peter Bonasso, David Kortenkamp, Troy Whitney
CPHYSICS
2010
135views more  CPHYSICS 2010»
13 years 10 months ago
An events based algorithm for distributing concurrent tasks on multi-core architectures
In this paper, a programming model is presented which enables scalable parallel performance on multi-core shared memory architectures. The model has been developed for application...
David W. Holmes, John R. Williams, Peter Tilke