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» The STEP Modular Architecture
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PPOPP
2010
ACM
14 years 3 months ago
Thread to strand binding of parallel network applications in massive multi-threaded systems
In processors with several levels of hardware resource sharing, like CMPs in which each core is an SMT, the scheduling process becomes more complex than in processors with a singl...
Petar Radojkovic, Vladimir Cakarevic, Javier Verd&...
CODES
2007
IEEE
14 years 3 months ago
Performance modeling for early analysis of multi-core systems
Performance analysis of microprocessors is a critical step in defining the microarchitecture, prior to register-transfer-level (RTL) design. In complex chip multiprocessor systems...
Reinaldo A. Bergamaschi, Indira Nair, Gero Dittman...
INFOCOM
2007
IEEE
14 years 2 months ago
A Framework for Multi-Objective SLA Compliance Monitoring
Abstract— Service level agreements (SLAs) specify performance guarantees made by service providers, typically in terms of packet loss, delay, delay variation, and network availab...
Joel Sommers, Paul Barford, Nick G. Duffield, Amos...
IISWC
2006
IEEE
14 years 2 months ago
Characterization of Error-Tolerant Applications when Protecting Control Data
Soft errors have become a significant concern and recent studies have measured the “architectural vulnerability factor” of systems to such errors, or conversely, the potentia...
Darshan D. Thaker, Diana Franklin, John Oliver, Su...
INFOCOM
2006
IEEE
14 years 2 months ago
Scheduling in Non-Blocking Buffered Three-Stage Switching Fabrics
— Three-stage non-blocking switching fabrics are the next step in scaling current crossbar switches to many hundreds or few thousands of ports. Congestion (output contention) man...
Nikolaos Chrysos, Manolis Katevenis