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» The Sizing Rules Method for Analog Integrated Circuit Design
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DAC
2009
ACM
14 years 8 months ago
Analysis and mitigation of process variation impacts on Power-Attack Tolerance
Embedded cryptosystems show increased vulnerabilities to implementation attacks such as power analysis. CMOS technology trends are causing increased process variations which impac...
Lang Lin, Wayne P. Burleson
ISVLSI
2008
IEEE
136views VLSI» more  ISVLSI 2008»
14 years 1 months ago
A Real Case of Significant Scan Test Cost Reduction
With the advent of nanometer technologies, the design size of integrated circuits is getting larger and the operation speed is getting faster. As a consequence, test cost is becom...
Selina Sha, Bruce Swanson
SBCCI
2005
ACM
114views VLSI» more  SBCCI 2005»
14 years 1 months ago
Traffic generation and performance evaluation for mesh-based NoCs
The designer of a system on a chip (SoC) that connects IP cores through a network on chip (NoC) needs methods to support application performance evaluation. Two key aspects these ...
Leonel Tedesco, Aline Mello, Diego Garibotti, Ney ...
KDD
2009
ACM
211views Data Mining» more  KDD 2009»
14 years 8 months ago
Address standardization with latent semantic association
Address standardization is a very challenging task in data cleansing. To provide better customer relationship management and business intelligence for customer-oriented cooperates...
Honglei Guo, Huijia Zhu, Zhili Guo, Xiaoxun Zhang,...
AMW
2010
13 years 9 months ago
Generating XML/GML Schemas from Geographic Conceptual Schemas
Abstract. A large volume of data with complex structures is currently represented in GML (Geography Markup Language) for storing and exchanging geographic information. As the size ...
André C. Hora, Clodoveu A. Davis Jr., Mirel...