A Real Case of Significant Scan Test Cost Reduction

With the advent of nanometer technologies, the design size of integrated circuits is getting larger and the operation speed is getting faster. As a consequence, test cost is becoming unbearable with traditional test methods. The big challenge for design and test engineers is how to guarantee the required high levels of test quality and yield while keeping the test cost low. From a scan-based ATPG point of view, there are two main ways to reduce test cost. One way is to reduce test pattern volume and test run time. The problem is how to maintain the same test coverage with a smaller test pattern set. The other way to reduce test cost is to use lower-end testers, which are much cheaper but have limited memory, data channels, and clocking capabilities. This paper shares the experiences of a real case of how to significantly reduce scan test cost by using DFT techniques.

• Type: Conference
• Year: 2008
• Where: ISVLSI
• Authors: Selina Sha, Bruce Swanson
• Keywords: ISVLSI 2008, Test Cost, Test Pattern, Traditional Test Methods, VLSI