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» The Structure and Performance of Interpreters
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HIPEAC
2007
Springer
15 years 10 months ago
Leveraging High Performance Data Cache Techniques to Save Power in Embedded Systems
Voltage scaling reduces leakage power for cache lines unlikely to be referenced soon. Partitioning reduces dynamic power via smaller, specialized structures. We combine approaches,...
Major Bhadauria, Sally A. McKee, Karan Singh, Gary...
ISCAS
2006
IEEE
110views Hardware» more  ISCAS 2006»
15 years 10 months ago
Network-on-chip link analysis under power and performance constraints
— This paper analyzes the behavior of interconnects in the highly structured environment of a network-on-chip (NoC). Two distinct classes of wires are considered, namely links be...
Manho Kim, Daewook Kim, Gerald E. Sobelman
PPOPP
2005
ACM
15 years 10 months ago
Performance modeling and optimization of parallel out-of-core tensor contractions
The Tensor Contraction Engine (TCE) is a domain-specific compiler for implementing complex tensor contraction expressions arising in quantum chemistry applications modeling elect...
Xiaoyang Gao, Swarup Kumar Sahoo, Chi-Chung Lam, J...
SBACPAD
2003
IEEE
102views Hardware» more  SBACPAD 2003»
15 years 10 months ago
Performance Analysis of DECK Collective Communication Service
Collective communication is very useful for parallel applications, especially those in which matrix and vector data structures need to be manipulated by a group of processes. This...
Rafael Ennes Silva, Delcino Picinin, Marcos E. Bar...
CCGRID
2002
IEEE
15 years 9 months ago
Representing Dynamic Performance Information in Grid Environments with the Network Weather Service
In this paper, we discuss requirements for integrating dynamic performance information from the Network Weather Service (NWS) into the Grid Information Service infrastructure (GIS...
D. Martin Swany, Richard Wolski