20 search results - page 2 / 4 » The Synchronization Power of Coalesced Memory Accesses |
ICCAD
2009
IEEE
13 years 5 months ago
2009
IEEE
Hardware acceleration is crucial in modern embedded system design to meet the explosive demands on performance and cost. Selected computation kernels for acceleration are usually ...
ISCA
2009
IEEE
14 years 2 months ago
2009
IEEE
The widespread use of multicore processors has dramatically increased the demands on high bandwidth and large capacity from memory systems. In a conventional DDR2/DDR3 DRAM memory...
OTM
2009
Springer
14 years 1 months ago
2009
Springer
Abstract. In this experience report, we present an evaluation of different techniques to manage concurrency in the context of application servers. Traditionally, using entity beans...
MICRO
2010
IEEE
13 years 5 months ago
2010
IEEE
SARC merges cache controller and network interface functions by relying on a single hardware primitive: each access checks the tag and the state of the addressed line for possible...
NOCS
2007
IEEE
14 years 1 months ago
2007
IEEE
The paper introduces Network-on-Chip (NoC) design methodology and low cost mechanisms for supporting efficient cache access and cache coherency in future high-performance Chip Mul...