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» The Synchronization Power of Coalesced Memory Accesses
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ACCESSNETS
2008
Springer
14 years 1 months ago
A Simulator of Periodically Switching Channels for Power Line Communications
An indoor power line is one of the most attractive media for in-home networks. However, there are many technical problems for achieving in-home power line communication (PLC) with ...
Taro Hayasaki, Daisuke Umehara, Satoshi Denno, Mas...
PODC
2010
ACM
13 years 11 months ago
The multiplicative power of consensus numbers
: The Borowsky-Gafni (BG) simulation algorithm is a powerful reduction algorithm that shows that t-resilience of decision tasks can be fully characterized in terms of wait-freedom....
Damien Imbs, Michel Raynal
SPDP
1993
IEEE
13 years 11 months ago
How to Share an Object: A Fast Timing-Based Solution
We consider the problem of transforming a given sequential implementation of a data structure into a wait-free concurrent implementation. Given the code for different operations ...
Rajeev Alur, Gadi Taubenfeld
SIAMCOMP
1998
117views more  SIAMCOMP 1998»
13 years 7 months ago
The Queue-Read Queue-Write PRAM Model: Accounting for Contention in Parallel Algorithms
This paper introduces the queue-read, queue-write (qrqw) parallel random access machine (pram) model, which permits concurrent reading and writing to shared memory locations, but ...
Phillip B. Gibbons, Yossi Matias, Vijaya Ramachand...
IWOMP
2007
Springer
14 years 1 months ago
Supporting OpenMP on Cell
The Cell processor is a heterogeneous multi-core processor with one Power Processing Engine (PPE) core and eight Synergistic Processing Engine (SPE) cores. Each SPE has a directly...
Kevin O'Brien, Kathryn M. O'Brien, Zehra Sura, Ton...