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105
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ICCAD
2005
IEEE
98views Hardware» more  ICCAD 2005»
16 years 13 days ago
Clustering for processing rate optimization
Clustering (or partitioning) is a crucial step between logic synthesis and physical design in the layout of a large scale design. A design verified at the logic synthesis level m...
Chuan Lin, Jia Wang, Hai Zhou
121
Voted
ISSS
1996
IEEE
102views Hardware» more  ISSS 1996»
15 years 7 months ago
Throughput Optimization in Disk-Based Real-Time Application Specific Systems
Traditionally, application specific computations have been focusing on numerically intensive data manipulation. Modern communications and DSP applications, such as WWW, interactiv...
Stephen Docy, Inki Hong, Miodrag Potkonjak
197
Voted
FPGA
2006
ACM
224views FPGA» more  FPGA 2006»
15 years 7 months ago
Flexible implementation of genetic algorithms on FPGAs
In this paper, we propose a technique to flexibly implement genetic algorithms for various problems on FPGAs. For the purpose, we propose a basic architecture for GA which consist...
Tatsuhiro Tachibana, Yoshihiro Murata, Naoki Shiba...
137
Voted
DAC
2007
ACM
16 years 4 months ago
Progressive Decomposition: A Heuristic to Structure Arithmetic Circuits
Despite the impressive progress of logic synthesis in the past decade, finding the best architecture for a given circuit still remains an open problem and largely unsolved. In mos...
Ajay K. Verma, Philip Brisk, Paolo Ienne
135
Voted
PR
2006
117views more  PR 2006»
15 years 3 months ago
On transforming statistical models for non-frontal face verification
: We address the pose mismatch problem which can occur in face verification systems that have only a single (frontal) face image available for training. In the framework of a Bayes...
Conrad Sanderson, Samy Bengio, Yongsheng Gao