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ISCA
2007
IEEE
146views Hardware» more  ISCA 2007»
14 years 1 months ago
Hardware atomicity for reliable software speculation
Speculative compiler optimizations are effective in improving both single-thread performance and reducing power consumption, but their implementation introduces significant compl...
Naveen Neelakantam, Ravi Rajwar, Suresh Srinivas, ...
ICS
2007
Tsinghua U.
14 years 1 months ago
Optimization of data prefetch helper threads with path-expression based statistical modeling
This paper investigates helper threads that improve performance by prefetching data on behalf of an application’s main thread. The focus is data prefetch helper threads that lac...
Tor M. Aamodt, Paul Chow
ICS
2007
Tsinghua U.
14 years 1 months ago
Sensitivity analysis for automatic parallelization on multi-cores
Sensitivity Analysis (SA) is a novel compiler technique that complements, and integrates with, static automatic parallelization analysis for the cases when relevant program behavi...
Silvius Rus, Maikel Pennings, Lawrence Rauchwerger
IWMM
2007
Springer
146views Hardware» more  IWMM 2007»
14 years 1 months ago
Allocation-phase aware thread scheduling policies to improve garbage collection performance
Past studies have shown that objects are created and then die in phases. Thus, one way to sustain good garbage collection efficiency is to have a large enough heap to allow many ...
Feng Xian, Witawas Srisa-an, Hong Jiang
LCTRTS
2007
Springer
14 years 1 months ago
Addressing instruction fetch bottlenecks by using an instruction register file
The Instruction Register File (IRF) is an architectural extension for providing improved access to frequently occurring instructions. An optimizing compiler can exploit an IRF by ...
Stephen Roderick Hines, Gary S. Tyson, David B. Wh...