193 search results - page 36 / 39 » The TigerSHARC DSP Architecture |
FCCM
1999
IEEE
14 years 3 months ago
1999
IEEE
Abstract We are developing an integrated algorithm analysis and mapping environment particularly tailored for signal processing applications on Adaptive Computing Systems ACS. Our ...
SIPS
2006
IEEE
14 years 4 months ago
2006
IEEE
Abstract— This paper presents a design environment for efficiently generating application-specific Intellectual Property (IP) cores for system level signal processing algorithm...
TCAD
2002
13 years 10 months ago
2002
In this paper, an instruction-level energy model is proposed for the data-path of very long instruction word (VLIW) pipelined processors that can be used to provide accurate power ...
PLDI
2003
ACM
14 years 4 months ago
2003
ACM
Clustered architectures are a solution to the bottleneck of centralized register files in superscalar and VLIW processors. The main challenge associated with clustered architectu...
ISVLSI
2007
IEEE
14 years 5 months ago
2007
IEEE
— We present a performance analysis of CoDeL, a highly efficient automated clock gating platform for rapidly developing power efficient hardware architectures. It automatically...