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    IPPS
    1998
    IEEE
    77views Distributed And Parallel Com...» more  IPPS 1998»
    Evaluating ASIC, DSP, and RISC Architectures for Embedded Applications
    14 years 3 months ago
    Evaluating ASIC, DSP, and RISC Architectures for Embedded Applications
    Download  ipdps.cc.gatech.edu
    Marc E. Campbell
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    DSD
    2009
    IEEE
    104views Hardware» more  DSD 2009»
    Simultaneous Multithreading VLIW DSP Architecture with Dynamic Dispatch Mechanism
    14 years 2 months ago
    Simultaneous Multithreading VLIW DSP Architecture with Dynamic Dispatch Mechanism
    Download  dsp.ime.tsinghua.edu.cn
    Zheng Shen, Hu He, Yihe Sun
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    ASPDAC
    1995
    ACM
    93views Hardware» more  ASPDAC 1995»
    Architectural simulation for a programmable DSP chip set
    14 years 2 months ago
    Architectural simulation for a programmable DSP chip set
    Download  www.cecs.uci.edu
    Jong Tae Lee, Jaemin Kim, Jae Cheol Son
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    DAC
    1995
    ACM
    174views Computer Architecture» more  DAC 1995»
    Conflict Modelling and Instruction Scheduling in Code Generation for In-House DSP Cores
    14 years 2 months ago
    Conflict Modelling and Instruction Scheduling in Code Generation for In-House DSP Cores
    Download  www.cecs.uci.edu
    Application domain specific DSP cores are becoming increasingly popular due to their advantageous trade–off between flexibility and cost. However, existing code generation metho...
    Adwin H. Timmer, Marino T. J. Strik, Jef L. van Me...
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    DAC
    1995
    ACM
    183views Computer Architecture» more  DAC 1995»
    Code Optimization Techniques for Embedded DSP Microprocessors
    14 years 2 months ago
    Code Optimization Techniques for Embedded DSP Microprocessors
    Download  reference.kfupm.edu.sa
    —We address the problem of code optimization for embedded DSP microprocessors. Such processors (e.g., those in the TMS320 series) have highly irregular datapaths, and conventiona...
    Stan Y. Liao, Srinivas Devadas, Kurt Keutzer, Stev...
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