Sciweavers

4679 search results - page 185 / 936
» The Timely Computing Base Model and Architecture
Sort
View
RTCSA
2008
IEEE
15 years 11 months ago
Concepts of Switching in the Time-Triggered Network-on-Chip
This paper presents the concepts of switching in the Time-Triggered Network-on-Chip (TTNoC), which is the communication subsystem of the Time-Triggered Systemon-Chip (TTSoC) archi...
Christian Paukovits, Hermann Kopetz
RAID
2010
Springer
15 years 2 months ago
CANVuS: Context-Aware Network Vulnerability Scanning
Enterprise networks face a variety of threats including worms, viruses, and DDoS attacks. Development of effective defenses against these threats requires accurate inventories of n...
Yunjing Xu, Michael Bailey, Eric Vander Weele, Far...
DAC
2000
ACM
16 years 5 months ago
Symbolic timing simulation using cluster scheduling
We recently introduced symbolic timing simulation (STS) using data-dependent delays as a tool for verifying the timing of fullcustom transistor-level circuit designs, and for the ...
Clayton B. McDonald, Randal E. Bryant
DAC
2004
ACM
16 years 5 months ago
Toward a systematic-variation aware timing methodology
Variability of circuit performance is becoming a very important issue for ultra-deep sub-micron technology. Gate length variation has the most direct impact on circuit performance...
Puneet Gupta, Fook-Luen Heng
VLSID
2000
IEEE
164views VLSI» more  VLSID 2000»
15 years 8 months ago
A Fast Algorithm for Computing the Euler Number of an Image and its VLSI Implementation
Digital images are convenient media for describing and storing spatial, temporal, spectral, and physical components of information contained in a variety of domains(e.g. aerial/sa...
Sabyasachi Dey, Bhargab B. Bhattacharya, Malay Kum...