Sciweavers

12334 search results - page 19 / 2467
» The Use of C
Sort
View
SUTC
2010
IEEE
13 years 8 months ago
Transaction-Level Modeling for Sensor Networks Using SystemC
—As sensor networks are finding widespread use across many applications, designers increasingly must not only focus on application development, but also on sensor network optimiz...
Jeff Hiner, Ashish Shenoy, Roman L. Lysecky, Susan...
ISCAS
2003
IEEE
118views Hardware» more  ISCAS 2003»
14 years 3 months ago
SoC design integration by using automatic interconnection rectification
the interconnection among the IP cores with all description levels This paper presents an automatic interconnection rectification (AIR)technique to correct the misplaced interconne...
Chun-Yao Wang, Shing-Wu Tung, Jing-Yang Jou
DAC
2012
ACM
12 years 7 days ago
A QoS-aware memory controller for dynamically balancing GPU and CPU bandwidth use in an MPSoC
Diverse IP cores are integrated on a modern system-on-chip and share resources. Off-chip memory bandwidth is often the scarcest resource and requires careful allocation. Two of t...
Min Kyu Jeong, Mattan Erez, Chander Sudanthi, Nige...
DATE
2003
IEEE
112views Hardware» more  DATE 2003»
14 years 3 months ago
Transaction-Level Models for AMBA Bus Architecture Using SystemC 2.0
The concept of a SOC platform architecture introduces the concept of a communication infrastructure. In the transaction-level a finite set of architecture components (memories, ar...
Marco Caldari, Massimo Conti, Massimo Coppola, Ste...
GLVLSI
2009
IEEE
151views VLSI» more  GLVLSI 2009»
14 years 1 months ago
Reliability aware NoC router architecture using input channel buffer sharing
To address the increasing demand for reliability in on-chip networks, we proposed a novel Reliability Aware Virtual channel (RAVC) NoC router micro-architecture that enables both ...
Mohammad Hossein Neishaburi, Zeljko Zilic