48 search results - page 8 / 10 » The Validity of Retiming Sequential Circuits |
ISPD
2003
ACM
14 years 29 days ago
2003
ACM
Traditional multilevel partitioning approaches have shown good performance with respect to cutsize, but offer no guarantees with respect to system performance. Timing-driven part...
AC
2002
Springer
13 years 7 months ago
2002
Springer
Abstract. Delay-Insensitive Sequential Processes is a structured, parallel programming language. It facilitates the clear, succinct and precise specification of the way an asynchro...
ISQED
2006
IEEE
14 years 1 months ago
2006
IEEE
— A methodology is proposed for interdependent setup time and hold time characterization of sequential circuits. Integrating the methodology into an industrial sign-off static ti...
GLVLSI
2003
IEEE
14 years 1 months ago
2003
IEEE
We introduce a simple hierarchical design technique for using dynamic domino circuits to build high-performance self-timed data path circuits. We wrap the dynamic domino circuit i...
ASPDAC
2007
ACM
13 years 11 months ago
2007
ACM
Clock skew scheduling is a technique that intentionally introduces skews to memory elements to improve the performance of a sequential circuit. It was shown in [21] that the full ...