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DAC
2004
ACM
14 years 9 months ago
Efficient on-line testing of FPGAs with provable diagnosabilities
We present novel and efficient methods for on-line testing in FPGAs. The testing approach uses a ROving TEster (ROTE), which has provable diagnosabilities and is also faster than ...
Vinay Verma, Shantanu Dutt, Vishal Suthar
CODES
2008
IEEE
14 years 3 months ago
Don't forget memories: a case study redesigning a pattern counting ASIC circuit for FPGAs
Modern embedded compute platforms increasingly contain both microprocessors and field-programmable gate arrays (FPGAs). The FPGAs may implement accelerators or other circuits to s...
David Sheldon, Frank Vahid
DATE
2010
IEEE
190views Hardware» more  DATE 2010»
14 years 25 days ago
Ultra-high throughput string matching for Deep Packet Inspection
Deep Packet Inspection (DPI) involves searching a packet's header and payload against thousands of rules to detect possible attacks. The increase in Internet usage and growing...
Alan Kennedy, Xiaojun Wang, Zhen Liu, Bin Liu
ANCS
2011
ACM
12 years 8 months ago
ReClick - A Modular Dataplane Design Framework for FPGA-Based Network Virtualization
Network virtualization has emerged as a powerful technique to deploy novel services and experimental protocols over shared network infrastructures. Although recent research has hi...
Deepak Unnikrishnan, Justin Lu, Lixin Gao, Russell...
DAC
2004
ACM
14 years 9 months ago
A method to decompose multiple-output logic functions
This paper shows a method to decompose a given multipleoutput circuit into two circuits with intermediate outputs. We use a BDD for characteristic function (BDD for CF) to represe...
Tsutomu Sasao, Munehiro Matsuura