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FPL
2004
Springer
112views Hardware» more  FPL 2004»
14 years 1 months ago
Automating the Layout of Reconfigurable Subsystems via Template Reduction
When designing SoCs, a unique opportunity exists to generate custom FPGA architectures that are specific to the application domain in which the device will be used. The inclusion o...
Shawn Phillips, Akshay Sharma, Scott Hauck
ISCAS
2003
IEEE
118views Hardware» more  ISCAS 2003»
14 years 1 months ago
Embedded reconfigurable array targeting motion estimation applications
Motion estimation is a complex computation found in video compression algorithms, such as standards like MPEG-4 and H.263. This paper proposes an embedded reconfigurable array for...
Sami Khawam, Tughrul Arslan, Fred Westall
DATE
2010
IEEE
161views Hardware» more  DATE 2010»
14 years 1 months ago
FPGA-based adaptive computing for correlated multi-stream processing
Abstract—In conventional static implementations for correlated streaming applications, computing resources may be inefficiently utilized since multiple stream processors may sup...
Ming Liu, Zhonghai Lu, Wolfgang Kuehn, Axel Jantsc...
ARC
2009
Springer
134views Hardware» more  ARC 2009»
14 years 1 months ago
A HyperTransport 3 Physical Layer Interface for FPGAs
Abstract. This paper presents the very first implementation of a HyperTransport 3 physical layer interface for Field Programmable Gate Arrays. HyperTransport is a low latency, high...
Heiner Litz, Holger Fröning, Ulrich Brün...
FPL
2009
Springer
101views Hardware» more  FPL 2009»
14 years 1 months ago
An accelerator for K-TH nearest neighbor thinning based on the IMORC infrastructure
The creation and optimization of FPGA accelerators comprising several compute cores and memories are challenging tasks in high performance reconfigurable computing. In this paper...
Tobias Schumacher, Christian Plessl, Marco Platzne...