862 search results - page 159 / 173 » The amorphous FPGA architecture |
DAC
2005
ACM
14 years 9 months ago
2005
ACM
In this paper we present a system level technique for mapping large, multiple-IP-block designs to channel-width constrained FPGAs. Most FPGA clustering tools [2, 3, 11] aim to red...
DAC
2006
ACM
14 years 9 months ago
2006
ACM
This paper describes an ultra low power active RFID tag and its automated design flow. RFID primitives to be supported by the tag are enumerated with RFID macros and the behavior ...
DAC
2006
ACM
14 years 9 months ago
2006
ACM
Transistor leakage is poised to become the dominant source of power dissipation in digital systems, and reconfigurable devices are not immune to this problem. Modern FPGAs already...
ICCD
2005
IEEE
14 years 5 months ago
2005
IEEE
FPGAs (Field-Programmable Gate Arrays) are often used as coprocessors to boost the performance of dataintensive applications [1, 2]. However, mapping algorithms onto multimillion-...
ICCAD
2006
IEEE
14 years 5 months ago
2006
IEEE
This work describes a new mapping technique, RAM-MAP, that identifies parts of circuits that can be efficiently mapped into the synchronous embedded memories found on field prog...