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» The amorphous FPGA architecture
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FPL
2009
Springer
135views Hardware» more  FPL 2009»
13 years 12 months ago
Fast critical sections via thread scheduling for FPGA-based multithreaded processors
As FPGA-based systems including soft processors become increasingly common, we are motivated to better understand the architectural trade-offs and improve the efficiency of these...
Martin Labrecque, J. Gregory Steffan
ASPDAC
2000
ACM
104views Hardware» more  ASPDAC 2000»
13 years 11 months ago
Design of digital neural cell scheduler for intelligent IB-ATM switch
— We present the architecture of the ATM banyan switch composed of pattern process and high-speed digital neural cell scheduler. An input buffer type ATM switch with a window-bas...
J.-K. Lee, Seung-Min Lee, Mike Myung-Ok Lee, D.-W....
ICCAD
1998
IEEE
109views Hardware» more  ICCAD 1998»
13 years 11 months ago
CORDS: hardware-software co-synthesis of reconfigurable real-time distributed embedded systems
Field programmable gate arrays (FPGAs) are commonly used in embedded systems. Although it is possible to reconfigure some FPGAs while an embedded system is operational, this featu...
Robert P. Dick, Niraj K. Jha
ARC
2006
Springer
122views Hardware» more  ARC 2006»
13 years 11 months ago
UNITE: Uniform Hardware-Based Network Intrusion deTection Engine
Abstract. Current software implementations of network intrusion detection reach a maximum network connection speed of about 1Gbps (Gigabits per second). This paper analyses the Sno...
Sherif Yusuf, Wayne Luk, M. K. N. Szeto, William G...
FPL
2006
Springer
108views Hardware» more  FPL 2006»
13 years 11 months ago
Implementation of Network Application Layer Parser for Multiple TCP/IP Flows in Reconfigurable Devices
This paper presents an implementation of a high-performance network application layer parser in FPGAs. At the core of the architecture resides a pattern matcher and a parser. The ...
James Moscola, Young H. Cho, John W. Lockwood