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FPGA
2001
ACM
152views FPGA» more  FPGA 2001»
13 years 12 months ago
A pipelined architecture for partitioned DWT based lossy image compression using FPGA's
Discrete wavelet transformations (DWT) followed by embedded zerotree encoding is a very efficient technique for image compression [2, 5, 4]. However, the algorithms proposed in l...
Jörg Ritter, Paul Molitor
IPPS
2007
IEEE
14 years 1 months ago
QUKU: A FPGA Based Flexible Coarse Grain Architecture Design Paradigm using Process Networks
DSP applications can be suitably represented using Process Network Models. This paper uses a modification of Kahn Process Network to solve the problem of finding an optimum arch...
Sunil Shukla, Neil W. Bergmann, Jürgen Becker
FPGA
1997
ACM
124views FPGA» more  FPGA 1997»
13 years 11 months ago
YARDS: FPGA/MPU Hybrid Architecture for Telecommunication Data Processing
This paper presents a novel system architecture applicable to high-performance and flexible transport data processing which includes complex protocol operation and a network contr...
Akihiro Tsutsui, Toshiaki Miyazaki
FPGA
2004
ACM
145views FPGA» more  FPGA 2004»
14 years 23 days ago
Exploration of pipelined FPGA interconnect structures
In this work, we parameterize and explore the interconnect structure of pipelined FPGAs. Specifically, we explore the effects of interconnect register population, length of regist...
Akshay Sharma, Katherine Compton, Carl Ebeling, Sc...
ICCAD
1994
IEEE
106views Hardware» more  ICCAD 1994»
13 years 11 months ago
On the NP-completeness of regular 2-D FPGA routing architectures and a novel solution
Several industrial FPGA routing architectures have been shown to have no efficient routing algorithms (unless P=NP) [3,4]. Here, we further investigate if the intractability of th...
Yu-Liang Wu, Douglas Chang