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FPGA
2008
ACM
168views FPGA» more  FPGA 2008»
13 years 8 months ago
Architectural improvements for field programmable counter arrays: enabling efficient synthesis of fast compressor trees on FPGAs
The Field Programmable Counter Array (FPCA) was introduced to improve FPGA performance for arithmetic circuits. An FPCA is a reconfigurable IP core that can be integrated into an ...
Alessandro Cevrero, Panagiotis Athanasopoulos, Had...
FPGA
2006
ACM
98views FPGA» more  FPGA 2006»
13 years 11 months ago
Efficient use of communications between an FPGA's embedded processor and its reconfigurable logic
Abstract-- Increasing device densities allow chip manufacturers to integrate more functionality onto a single piece of silicon. FPGA manufacturers, such as Xilinx and Altera, use t...
Joshua Noseworthy, Miriam Leeser
FPL
2009
Springer
166views Hardware» more  FPL 2009»
13 years 12 months ago
Modeling post-techmapping and post-clustering FPGA circuit depth
This paper presents an analytical model that relates FPGA architectural parameters to the expected speed of FPGA implementation. More precisely, the model relates the lookuptable ...
Joydip Das, Steven J. E. Wilton, Philip Heng Wai L...
FPGA
2008
ACM
155views FPGA» more  FPGA 2008»
13 years 9 months ago
A novel FPGA logic block for improved arithmetic performance
To improve FPGA performance for arithmetic circuits, this paper proposes a new architecture for FPGA logic cells that includes a 6:2 compressor. The new cell features additional f...
Hadi Parandeh-Afshar, Philip Brisk, Paolo Ienne
FPGA
2005
ACM
122views FPGA» more  FPGA 2005»
14 years 26 days ago
Power modeling and architecture evaluation for FPGA with novel circuits for Vdd programmability
Vdd-programmable FPGAs have been proposed recently to reduce FPGA power, where Vdd levels can be customized for different circuit elements and unused circuit elements can be powe...
Yan Lin, Fei Li, Lei He